1. Field of the Invention
In semiconductor memory arrays in which further circuits are also integrated on the same chip in addition to the actual memory region, such as in picture memories, there is a demand for ever-increasing data rates and/or a greater number of circuits for further processing data on the same chip. Since the speed of access to the memory region, which is usually constructed as a DRAM, cannot be increased at will, more and more bits must be transmitted simultaneously and parallel to or from the memory region upon each access.
Conventional standard DRAMs today operate with up to 16 internal, parallel double data lines. One such double data line includes two parallel data lines, with each of the two carrying a signal complementary to that of the other data line. This provision makes it possible to attain a fast switching time for the read amplifiers and therefore a shorter signal transit time from the actual memory region to the data accesses of a memory array.
However, picture memories should offer blocks of up to 32.times.9=288 bits simultaneously with random access from or to a 4 Mb cell field, to or from a plurality of data accesses with buffer memories and shift registers. If a double data line including two data lines were used, that would mean 576 parallel lines for the example given.
It is accordingly an object of the invention to provide an integrated semiconductor memory array, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and which reduces the number of necessary lines at a high data rate.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor memory array, comprising a memory region having a plurality of segments, each of the memory region segments having a plurality of read amplifiers, and bit lines, each two of the bit lines being connected to a respective one of the read amplifiers; a plurality of parallel data lines leading to the memory region, each of the data lines having an end oriented toward and another end oriented away from, a respective one of the memory region segments; read/write amplifier switches each being disposed at a different one of the ends of a respective one of the data lines; and selector switches each connecting the read/write amplifier switch disposed on the end of a respective one of the data lines oriented toward the memory region segment to a respective one of the read amplifiers of the memory region segment.
Accordingly, in the integrated semiconductor memory array according to the invention, only a single data line is used instead of a double data line, with read/write amplifier switches disposed at both ends of this data line. Since the length of these data lines is often considerable, and they furthermore have an extensive capacitance coating, the signals to be transmitted subsequently must be amplified before being transmitted. Since these data lines are used bidirectionally, amplifiers are necessary on both ends of the data lines, with one of the amplifiers being used for the reading mode and the other for the writing mode of the memory array. Besides the amplifiers, switches are also provided, in the read/write amplifier switches, with the aid of which the signals in the operating mode for which the amplifiers are not intended are made to bypass the amplifiers.
In accordance with another feature of the invention, the read/write amplifier switches disposed on the end of the data lines oriented away from the memory region are connected to one or more circuit configurations, and when there are a plurality of circuit configurations for further processing data, these configurations are connected through selector switches to the various read/write amplifier switches.
In accordance with a further feature of the invention, the circuit configurations for further processing data are constructed as buffer memories or shift registers or data input/output circuits. However, other circuit configurations are also conceivable.
Since two bit lines each with complementary information are present inside the memory region, these bit lines may be reduced to one data line in either the read amplifiers or the read/write amplifier switches. In accordance with a concomitant feature of the invention, the read/write amplifier switches are thus connected through either one or two connecting lines with the applicable memory region segments and with the circuit configurations for further processing data.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor memory array, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.